1. Field of the Invention
The present invention generally relates to computer systems, and more particularly to a method of guardband testing for a system having a critical path monitor used to optimize processor frequency.
2. Description of the Related Art
Electronic devices such as computer systems or their components must be tested for quality control purposes to ensure that the product as shipped will function as intended. However, all testing methodologies have their limitations and can still result in mischaracterization of performance, for example, due to measurement errors, or due to process or environmental variations. In order to provide additional assurance of proper operation, designers build a safety margin into product specifications such as lower frequency or higher voltage. This additional safety margin is referred to as a guardband. The guardband thus ensures that even with testing uncertainty and worst case environment the product meets the stated minimum specifications with a high degree of confidence.
While guardbands can guarantee proper operation under most conditions, they have several disadvantages. When guardbands are added, some devices that would have otherwise passed quality control testing will end up failing. Thus, from the standpoint of yield, the smaller the guardband the better. Guardbands can also lead to inefficient operation of the device. For example, process, voltage, and temperature variations cause timing variation within an integrated circuit design such as a microprocessor and the guardband must be such that it protects the absolute worst case that can theoretically occur, making it necessary to provide timing margins that compromise the potential performance of the device.
In a processor core, the maximum frequency of the processor clock is dictated by the delay of a critical path within the processor, that is, a path that, at the present operating temperature and voltage, will cause the processor to fail when the frequency of the processor clock is raised above a particular limit. The critical path may be a single critical path for all operating conditions, or the critical path may change, for example, at different operating temperatures or at different voltages. Critical path monitor (CPM) circuits have been implemented that simulate the critical path or paths, and provide information regarding the critical path delay of a processor or other integrated circuit device. CPMs can synthesize critical path timing through such delay elements as wired interconnects within the IC and/or logic gates of the IC, and provide information to a phase-locked loop that generates the processor clock to provide real-time feedback of variations in the critical path delay, e.g., variation of the critical path delay with dynamic changes in the power supply voltage at particular locations within the integrated circuit device. CPMs thus allow reduction in margin (guardband) for thermal and voltage conditions in the system instead of having to always account for worst case conditions, and thereby increase operational efficiency.
FIG. 1 illustrates the basic components for one example of a CPM circuit 2 which include a pulse generator 3, a calibration delay 4, a critical path synthesis 5, and an edge detector 6 to implement a timing-margin-to-digital conversion function. Pulse generator 3 receives a signal from the clock core and creates a timing edge synchronized to the system clock. The timing edge passes through calibration delay 4 which is used to compensate for process variation, operating point changes, and margin variation at different frequencies, and then through critical path synthesis 5 which will track with (mirror) the overall processor circuit margin. After passing through the synthesis block, the edge is latched in the edge detector by the system clock. The delay from pulse generation to edge detection is typically one clock cycle but can be multiple clock signals to improve accuracy. After the edge detector there is some signal conditioning and two output signals. An encoder 7 is used to generate a 5-bit window of the 12-bit edge detector which is then fed directly to a digital phase-lock loop (DPLL) and is used to adjust frequency to respond to changes in timing margin. The edge detector is essentially a delay line with latch elements attached at each interval. As the timing signal progresses along this delay line it flips the latch bits from 0 to 1. The location of the 1-to-0 transition that occurs when the system clock arrives marks the timing point for a given cycle. The timing margin at a given cycle is the difference between the current CPM bit position and the calibration bit position.
Calibration of the CPM is key to ensuring proper frequency and timing margin. In this example, CPMs are calibrated by adding or subtracting calibration delay from the circuit until the DPLL achieves a target frequency at a given voltage, temperature, and workload. A valid production calibration point is found by measuring the delay of the synthesis path required to achieve the target frequency. Calibration is typically done at both ends of the intended voltage operating range. Calibration inaccuracy can occur and falls into two categories. The first is variation between the tester and the system running the same conditions and workload. The second is driven by the fact that a limited number of calibrations points (usually one) need to control the CPM through the full operational voltage range. By comparing the calibration result collected at the two voltage points the designer can measure how well the CPM tracks with the tester measured frequency. Any variation will result in divergence from the target frequency over changing voltage leading to excessive or insufficient margin.